The present invention relates to processes for the fabrication of very small integrated bipolar transistors, and more particularly to a self-aligned process for fabricating a bipolar transistor with polysilicon contacts.
The trend in semiconductor technologies is toward large scale integration of devices with very high speed, high packing density and low power dissipation. Jointly achieving these characteristics always involves trade-offs, particularly between speed and power dissipation and between power dissipation and packing density.
In general, to achieve the objectives of high packing density, high speed and low power, it is essential that these devices be made as small as possible. In both bipolar and field-effect transistor technologies, it is desirable to reduce the horizontal geometry of the devices. In FET technologies, design objectives focus primarily on reducing gate length, which serves both to reduce the horizontal geometry of the device and to increase its speed of operation. In bipolar technologies, it is desirable to reduce both emitter area and the depth of the vertical junction structure.
Device horizontal geometry depends largely on the photolithographic techniques and tools available. The resolution provided by a particular photolithographic process determines the minimum feature size that can ordinarily be made in each masking step. Additionally, at very small feature sizes, alignment between mask steps becomes very critical. Although improvements continue to be made, conventional photolithography provides reliable resolution down to just under 2 um. Similarly, obtaining alignment tolerances much below 0.5 um. is very difficult with conventional equipment. As a result, obtaining an economic yield of operative devices becomes very difficult both as device size is reduced and as number of devices per chip is increased.
One of the early attractions of metal-oxide-semi-conductor (MOSFET) technology stems from its simplicity, both in number of masking process steps needed to fabricate a device and in the relative ease of obtaining self-alignment between the gate electrode and adjoining diffused regions in the substrate. An example of such technology is shown in L.L. Vadasz et al., "Silicon-gate technology," IEEE Spectrum, October 1969, pages 28-35. More recent MOSFET technology additionally provides self-aligned source and drain electrodes, as shown for example in C.S. Oh, et al., "A New MOSFET Structure with Self-Aligned Polysilicon Source and Drain Electrodes," IEEE Electron Device Letters, Vol. EDL-5, No. 10, October 1984, pages 400-402.
Notwithstanding the improvements shown by comparison of the above-cited references, size and alignment concerns are essentially one dimensional in MOSFET technologies. The width of the gate of FET devices is essentially a matter of design choice. Current MOS technology enable very large scale integrated (VLSI-over 10,000 gates per chip) circuits to be built with a high packing density and with low power requirements. Moreover, VLSI MOS circuits can be produced with a very high yield, commonly around 30%.
The primary disadvantage of MOS technologies, when compared to bipolar technologies, is speed. In MOS devices, gate delays commonly exceed one nanosecond when loaded, especially with a capacitive load. In contrast, bipolar devices can maintain gate delays of about one half nanosecond or better when capacitively loaded.
Bipolar technologies have generally lacked the advantages of MOS technologies. Bipolar devices generally require substantially more power than MOS devices. They also typically require substantially more substrate area per device. Conventional bipolar technologies using emitter-coupled logic (ECL) typically produce transistor areas of over 250 um..sup.2 and dissipate over 10 mW per gate (5 mW per equivalent gate) when operated at speeds providing system propagation delays of 300-500 ps. Common packaging technologies limit total chip power dissipation to around 10W. These factors result in a substantially lower packing density than MOS devices, limiting bipolar densities to less than 10,000 transistors per chip or about 3000 gates (compared to 10-20,000+ for CMOS), or a substantial tradeoff in speed. Also, because of their complexity, prior bipolar technology yields are low compared to MOS technologies by a factor of two or more (10-15%).
Consequently, commercial scale bipolar technologies have been largely limited to large scale integrated (LSI) circuit packing densities. Bipolar transistors produced by conventional LSI technologies typically have a cutoff frequency f.sub.t of around 3 GHz at 2mA and exhibit 50fF of junction capacitance.
In processing a substrate to fabricate a bipolar device, the designer may choose between an epitaxial or a triple diffusion technology. The epitaxial process predominates in commercial use. Examples of epitaxial processes are shown in U.S. Pat. No. 4,381,953 to Ho et al., U.S. Pat. No. 4,483,726 to Isaac et al., U.S. Pat. No. 4,433,471 to Ko et al., U.S. Pat. No. 4,495,010 to Kranzer et al. and in "A Bipolar Process That's Repelling CMOS," Electronics, Dec. 23, 1985, pages 45-47. Examples of triple diffusion technology are described in U.S. Pat. No. 4,276, 543 to Miller et al., R. Wolfle, "Fast High-Voltage Silicon Triple-Diffused Power Transistors," Siemens Review XXXIX (1972) No. 8, pages 370-373, and in S. Konaka et al., "A 30 ps Si Bipolar IC Using Super Self-Aligned Process Technology," Extended Abstracts of the 16th (1984 International) Conference on Solid State Devices and Materials, Kobe, 1984, pages 209-212. An analysis of characteristics of epitaxial and triple-diffused transistors appears in W.J. Chudobiak, " On the Static Collector-Emitter Saturation Voltage of a Transistor with a Lightly Doped Collector," Proceedings of the IEEE, April 1969, pages 718-720.
The designer also has a number of choices of how to define various device features, such as active transistor area. Photolithographic techniques are widely used but, as mentioned above, are limited to the resolution of photolithography. In the fabrication of discrete bipolar devices, it is also known to employ controlled undercut techniques to form device features smaller than those provided by photolithography. This technique is described by F. Morandi et al., in "Controlled Undercut Microwave Devices," SGS-Fairchild, S.p.A., Milan, Italy, International Electron Devices Meeting, 23-25 October 1968, Washington, D.C. (abstract published by IEEE 1968), page 108.
Various techniques are conventionally used in MOS technologies to define the device regions as well as to provide insulative field oxide layers over regions between devices. One is the LOCOS technique, described by J.A. Appels et al., "Local Oxidation of Silicon; New Technological Aspects," Philips Research Reports, Vol. 26, No. 3 (June 1971), pages 157-165, and by J.S. Makris et al., "Forming Fine-Line Geometries in Integrated Circuits," IBM Technical Disclosure Bulletin, Vol. 16, No. 10 (March 1974), pages 3240-3241. J.A. Appels et al. also disclose the use of controlled under-etching of nitride-oxide sandwich structures (LOCOS-II method) in the preparation of MOS transistors. The LOCOS method, however, requires an extended heat cycle to grow the thick layer of thermal oxide. This is explicitly avoided in fabricating bipolar transistors in U.S. Pat. No. 4,381,953 (column 3, lines 5-6). Current bipolar technologies--exemplified by the Ho et al., Isaac et al. and Ko et al. patents and the Konaka et al. article--instead use various, planar etch-and-refill isolation techniques. A variation of such techniques that has been tried by Texas Instruments and Siemens (see Kranzer et al.) as a way to increase bipolar packing densities is trench isolation, reported in the "Electronics" article cited above.
Most of the efforts to solve alignment problems in both MOS and bipolar technologies have been directed to self-aligned processes. Various self-aligned processes are described in the patents cited above. State of the art in both MOS (see Ho et al.) and bipolar (see Oh et al.) technologies use a polysilicon layer patterned to form a gate or contact. This layer is covered by an insulative oxide box structure formed by silicon dioxide deposition or thermal growth followed by reactive ion etching. The box structure serves as a self-aligned mask in later ion-implantation steps.
In conventional bipolar processes, the active device features are generally formed as a square or nearly square emitter region concentrically positioned within a collector region of similar geometry. The self-alignment techniques strive to form the horizontal features in both dimensions and for several process steps using a single photolithographic mask. Deposition of polysilicon on the substrate surface followed by out-diffusion of the dopant impurities into the substrate or epitaxial layer has also been used in these self-aligned techniques. The above-cited patent to Oh et al. uses this technique to form base regions self-aligned with base contacts provided by the polysilicon. Konaka et al., cited above, discloses use of a highly-doped polysilicon emitter contact to form a diffused emitter.
In epitaxial processes, such as Ko et al. and Kranzer et al., it is conventional to use an N-type buried layer under the epitaxial layer to reduce collector resistance Rcx between the collector contact region and the active device region. The effectiveness of this approach decreases, however, as lateral device dimensions become smaller relative to vertical spacing between the active device and the buried layer. This approach also makes alignment of subsequent masking steps difficult, with attendant difficulties in obtaining economic yields, and increases collectorsubstrate capacitance Ccs, which tends to slow device operation. A triple diffused process, such as Miller et al., may increase yield but sacrifice speed, due to increased collector-base capacitance Ccb, and reduced saturation current, due to increased collector resistance Rcx. Conventional approaches to reducing collector-base capacitance by narrowing the emitter and base also tends to increase base resistance Rbx. Attempting to reduce collector resistance similarly tends to increase collector-substrate capacitance Ccs. Thus, significant tradeoffs are presented to the designer in selecting between conventional bipolar processes and, within a given process, between various performance parameters.
So far as known, no prior integrated circuit fabrication process has been devised that will enable operative very large scale integrated (VLSI) bipolar circuits to be made with both high density, speed and yield and low power. Accordingly, a need remains for a bipolar integrated circuit technology that will enable commercially-feasible, very large scale integration of bipolar circuitry.